Physical Design Engineer

**Position : Physical Design Engineer
Location : Palo Alto, CA (Full Onsite)
Number of Positions : 5 **

JD for PD:

• Exposure to TSMC 2NP/3NP is must
• Perform end to end physical design flow:
o Floorplanning
o Power planning (PG grid, IR)
o Placement & optimization
o CTS (Clock Tree Synthesis)
o Routing
o Post route optimization
• Achieve timing closure across all modes and corners
• Resolve DRC, LVS, ERC and signoff violations
• Handle low power design techniques:
o Multi Vt, Multi voltage (UPF)
o Power gating, clock gating
• Perform physical verification and signoff:
o STA (Primetime)
o SI / Crosstalk
o IR drop & EM analysis
• Work on advanced nodes (7nm, 5nm, 3nm or below)
• Collaborate with:
o RTL & Micro architecture teams
o DFT & Test engineers
o Foundry and CAD teams
• Debug complex timing, congestion, power, and variability issues
• Drive methodology improvements and automation (scripts/flows)